With explosive growth of mobile communication apparatus, there is a strong demand for smaller and less costly wireless apparatus. Consequently, application of a transceiver integrated circuit (IC) with enhanced integration is hoped for. One example of the transceiver IC with improved integration by prior art is a direct-conversion transceiver IC introduced by Hitachi, Ltd. in 2001 (see non-patent document 1). This uses an offset PLL transmitter circuit and, in the transmitter, there are an RF frequency band phase-locked loop (PLL), an intermediate frequency (IF) band PLL, and a transmission oscillator; altogether three oscillation circuits and PLL circuits including oscillators.
A mobile phone configuration that uses a modulation type fractional divider PLL frequency synthesizer in which a digital dither circuit is provided between a digital input and a delta-sigma (ΔΣ) modulator to supply a digital output which discretely changes from the digital input with its time-average corresponding to the digital input to the delta-sigma (ΔΣ) modulator is known (e.g., see patent document 1). Since the “delta-sigma modulator” is generally called a “sigma-delta (ΣΔ) modulator,” the term “sigma-delta (ΣΔ) modulator” will be used hereinafter.
[Patent document 1] Japanese Patent Laid-Open No. 2002-152044
[Non-patent document 1] S. Tanaka et al., “GSM/DCS1800 Dual Band Direct-Conversion Transceiver IC,” Proceedings of the 27th European Solid-State Circuits Conference pp. 492-495, 2001